This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. xc2xa7119 from my application entitled COMPUTER SYSTEM CONTROLLING MEMORY CLOCK SIGNAL AND METHOD FOR CONTROLLING THE SAME earlier filed with the Korean Industrial Property Office on Oct. 16, 1998 and there duly assigned Serial No. 43756/1998.
1. Field of the Invention
The present invention relates to computer systems generally, and, more particularly, to a computer system and process for controlling memory clock signals.
2. Related Art
A system bus of a computer system is an operational path where a central processing unit (i.e., a CPU), a memory, and peripheral devices transmit data to one another. For example, a 100 mega-Hertz system bus transmission speed means that data is transmitted at a speed of 100 mega-Hertz. Chipset manufacturing companies intending to improve system bus speed have indicated that the current 66 MHz system bus transmission speed (often refer to as xe2x80x9cPC 66xe2x80x9d) can not keep up with the increasing speed of the newer generations of central processing units.
Recent efforts in the art include U.S. Pat. No. 5,680,595 to Thomann et al. entitled PROGRAMMABLE DATA PORT CLOCKING SYSTEM FOR CLOCKING A PLURALITY OF DATA PORTS WITH A PLURALITY OF CLOCKING SIGNALS IN AN ASYNCHRONOUS TRANSFER MODE SYSTEM, issued Oct. 21, 1997; U.S. Pat. No. 5,509,138 to Cash et al, entitled METHOD FOR DETERMINING SPEEDS OF MEMORY MODULES, issued on Apr. 16, 1996; U.S. Pat. No. 5,761,533 to Aldereguia et al., entitled COMPUTER SYSTEM WITH VARIED DATA TRANSFER SPEEDS BETWEEN SYSTEM COMPONENTS AND MEMORY, issued on Jun. 21, 1998; U.S. Pat. No. 5,862,368 to Miller et al., entitled PROCESS TO ALLOW AUTOMATIC MICROPROCESSOR CLOCK FREQUENCY DETECTION AND SELECTION, issued on Jan. 19, 1999, U.S. Pat. No. 5,887,146 to Baxteretal., entitled SYMMETRIC MULTIPROCESSING COMPUTER WITH NON-UNIFORM MEMORY ACCESS ARCHITECTURE, issued on Mar. 23, 1999; U.S. Pat. No. 5,903,747 to Casal, entitled MICROPROCESSOR CLOCKING CONTROL SYSTEM, issued on May 11, 1999; U.S. Pat. No. 5,903,916 to Pawlowski et al., entitled COMPUTER MEMORY SUBSYSTEM AND METHOD FOR PERFORMING OPPORTUNISTIC WRITE DATA TRANSFERS DURING AN ACCESS LATENCY PERIOD WITHIN A READ OR REFRESH OPERATION, issued on May 11, 1999; and U.S. Pat. No. 5,522,064 to Aldereguia et al., entitled DATA PROCESSING APPARATUS FOR DYNAMICALLY SETTING TIMING IN A DYNAMIC MEMORY SYSTEM, issued on May 28, 1996. The efforts proposed by these references are, in my opinion, unsatisfactory. Aldereguia et al, U.S. Pat. No. 5,522,064 for example, proposes to use a programmable memory controller to store information that defines the timing requirements of each of the modules.
In an effort to address the perceived need for a system bus with a transmission speed that is more compatible with the newer microprocessors, Intel Corporation has developed a 100 MHz system bus transmission speed (often referred to below as xe2x80x9cPC 100xe2x80x9d) in response to the fast developing speed of a CPU. That is, the PC 100 has a system bus transmission speed that is able to operate at 100 MHz. For example, the PC 100 can be used in a main board having with an Intel 440BX chipset driven by a high speed CPU such as a Pentium II microprocessor operating at 350 MHz.
The PC 100 system bus has two significant advantages. The first advantage is an improvement in system performance. For example, the operational time of a 66 MHz system bus is 66xc2x7105/seconds. With the PC 100 system bus, 64 bits are operated upon at one time and 8 bits are equal to 1 byte, 528 MB/second may be transmitted via the PC 66 system bus. On the other hand, the operation time of a 100 MHz system bus is 108/seconds. Thus, 800 MB/sec is transmitted via the PC 100 system bus, an improvement of data transmission speed of 51%.
The second advantage is the stability of peripheral devices that are used in conjunction with a PC 100 system bus. Since the processing speed of the 66 MHz system bus is too fast, a peripheral component interconnection bus (i.e., a PCI bus) is operated at 33 MHz/sec. Therefore, peripheral devices such as a graphic card and a hard disk drive are operated at 33 MHz. If a PC 66 system bus is converted by overclocking the bus from 66 MHz to 100 MHz, the PCI bus will be operated at 37.5 MHz (i. e., 13% over PCI limitations). Therefore, operational and functional errors such as shutdown may be generated by the overclocking of the PC 66 system bus. With a PC 100 system bus however, the PCI bus is operated at ⅓ of the clock speed (i.e., at 33.3 mega-Hertz), so that 33.3 MHz operational frequency of the PCI bus meets the PCI standard. Despite the use of a high system bus clock, high speed peripheral devices can still be stably used. Moreover, the 100 MHz system bus will be able to accommodate a high speed CPU of the next generation of microprocessors.
Despite these efforts in the art, I have found that it is conventional practice to either continuously supply clock signals to vacant memory module sockets or, when the memory clock signal to an unoccupied dual in line memory module socket is terminated, the unused memory clock signals are continuously supplied to the memory modules mounted in the occupied sockets. Consequently, computer systems subjected to conventional clock signal protocol are often unnecessarily exposed to electromagnetic interference (i.e., EMI). Thomann, U.S. Pat. No. 5,680,595, in an effort to provide a programmable data port clocking system, for example, relies upon mode storage to supply the setting data for a memory module, a mode decoder that decodes the setting data to provide a plurality of signals that correspond to a least one transfer mode, a mode controller that regulates the clock signal for the transfer mode that is output in response to the output signals, and a switching stage that outputs clock signals to a plurality of ports in response to the clock signal. Cash, U.S. Pat. No. 5,509,138, attempts to provide memory access in accordance with the different speeds of the memory modules, but requires the reading of the setting data defining the size, speed and composition code of the memory module, a decision about the position of data for the memory module, and the storage of the speed of the memory module whenever the memory module is included in the entry and the storage of a lowest speed for the memory module when that module is not included in the entry. These systems are not particularly simple and require more than a single operational cycle to implement.
It is therefore an object of the present invention to provide an improved computer system.
It is another object to reduce the exposure of a computer system to electromagnetic interference.
It is still another object to provide a computer system and process able to terminate application of memory clock signals to vacant memory module sockets.
It is yet another object to provide a computer system and process able to terminate application of unnecessary memory clock signals to occupied memory module sockets.
It is still yet another object to provide a computer system and process able to automatically terminate the application of memory clock signals to an occupied memory module socket that do not conform to the bus speed of the memory module occupying that socket.
It is a further object to provide a computer system an process able to automatically adjust the application and frequency of the memory clock signals applied to each of a plurality of memory module sockets to conform to determinations of whether each socket is occupied, to determinations of the type of memory module that is resident within each socket, and to determinations of the bus speed of each memory module that is resident within each socket.
It is a still further object to implement a computer system and process that is able to cut off a clock signal to an unused memory module socket of a computer system and an unused clock signal among the clock signals being applied to a memory module socket that is in use.
It is a yet further object to provide a computer system and control process capable of interrupting an unused clock signal to a corresponding module type of a mounted memory module.
It is a still yet further object to implement a computer system and process of controlling memory clock signals for the computer system.
It is also an object to provide a computer system and process of adjusting memory clock signals applied to memory modules to conform to the type of memory module and the corresponding bus speed of the memory module.
It is an additional object to provide a simple, and readily implementable computer system and process of applying memory clock signals that conform to the type of memory module and the corresponding bus speed of the memory module within each of a plurality of memory module sockets.
It is a still additional object to provide a computer system and process able to both terminate memory clock signals to vacant memory module sockets and to terminate unnecessary memory clock signals to occupied memory module sockets.
These and other objects may be attained according to the principles of the present invention, with a computer system and control process using a processor that provides a control signal to generate a first or a second bus clock signal and at least one memory module, constructed with a first system controller reading main data from the memory module and then generating setting data corresponding to the memory data; and a clock generator responding to reception of the control signal by providing a first or a second host clock signal corresponding to the setting data. A second system controller responds to reception of the first or second host clock signal by generating a first or a second reference clock signal that is referenced to a memory clock signal for the memory module, and a clock buffer receives the first or the second reference clock signal and then generates first through fourth memory clock signals corresponding to the setting data for the memory module. If the memory module is a single-sided type memory module, the clock buffer cuts off unused memory clock signals for the single-sided memory module among the first to the fourth memory clock signals through the setting data.
The first system controller may transmit the memory data and the setting data through a system management bus (i.e., a SM bus). The clock generator and the clock buffer may include a register that stores the setting data. If the memory module is a single-sided type memory module, a clock buffer may disable the second memory clock signal and the fourth memory clock signal when the first reference clock signal is received, and may disable the third memory clock signal and the fourth memory clock signal when the second reference clock signal is received.
According to the present invention, a process for using a computer system to control a memory clock signal to at least one dual in-line memory module (i. e., a DIMM), may enable the first through fourth memory clock signals to all memory sockets, determine whether a memory module is inserted into a socket among the enabled memory sockets; determine the kind of the inserted memory module that has been inserted into each of the enabled memory sockets, if any memory module has been inserted into any of the memory sockets; and maintain enablement of the first to fourth memory clock signals to a memory socket when the memory module in that socket is determined to be a double-sided type memory module. If the memory module within the memory socket is found to be a single-sided memory module, a determination is made of whether the bus speed of the memory module is the first speed or the second speed. Memory clock signals corresponding to the second speed for the memory module among the first to the fourth memory clock signals are disabled when the bus speed for the resident memory module is determined to be the first speed; and memory clock signals corresponding to the first speed of the memory module among the first to the fourth memory clock signals are disabled when the bus speed corresponding to the resident memory module is determined to be the second speed. With one embodiment of the present invention, if no memory module is found to have not been inserted into a memory module socket (that is, if the socket is unoccupied by a memory module), the first through the fourth memory clock signals for that memory module socket are disabled.
Thus, in the practice of the present invention, a microprocessor is able to determine whether a memory module has been inserted into a memory module socket with the processing steps of the basic input and output system (i.e., the BIOS) and then read memory data for a memory module where a system controller is determined. The microprocessor may store the memory data read in a clock generator and a clock buffer. As a result, an unused clock signal for a resident memory module is controlled in conformity with the kind of memory module found to be inserted into the memory module socket and in response to either a first or a second system bus clock signal.